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2.7 v to 5.5 v, <100 a, 8 - /10 - /12 - bit nano dac, spi interface in lfcsp and sc70 data sheet ad5601 / ad5611 / ad5621 rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specif ications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 C 2012 analog devices, inc. all rights reserved. features 6 - lead sc70 and lfcsp package s micropower operation: 100 a max imum at 5 v power - down typically to 0.2 a at 3 v 2.7 v to 5.5 v power supply guaranteed monotonic by design power - on reset to 0 v with brownout detection 3 power - down functions low power serial interface with schmitt - triggered inputs on - chip output buffer amplifier, rail - to - rail operation sync interrupt facility minimized zero - code error a d5601 buffered 8 - bit dac b version: 0.5 lsb inl ad5611 buffered 10 - bit dac b version: 0.5 lsb inl a version: 4 lsb inl ad5621 buffered 12 - bit dac b version: 1 lsb inl a version: 6 lsb inl applications voltage level setting portable battery - powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators general description the ad5601/ad5611/ad5621, members of the nano da c ? family, are single, 8 - /10 - /12 - bit, buffered voltage out put dacs that operate from a single 2.7 v to 5.5 v supply, consuming typically 7 5 a at 5 v. the parts come in tiny lfcsp and sc70 package s . their on - chip precision output amplifier allows rail - to - rail output swing to be achieved. the ad5601/ad5611/ ad5621 ut ilize a versatile 3 - wire serial interface that operates at clock rates up to 30 mhz and is compatible with spi , qspi?, microwire?, and dsp interface standards. the reference for the ad 5601 /ad 5611 /ad 5621 is derived from the power supply inputs and, theref ore, gives the widest dynamic output range. the parts incorporate a power - on reset circuit, which ensures that the dac output powers up to 0 v and remains there until a valid w rite to the device takes place. the ad5601/ad5611/ad5621 contain a power - down fe ature that reduces current consumption to typically 0.2 a at 3 v. functional block dia gram figure 1. table 1 . related devices part number description ad5641 2.7 v to 5.5 v, <100 a, 14 - bit nano dac in sc70 and lfcsp package s they also provide software - selectable output loads while in power - down mode. the parts are put into power - down mode over the serial interface. the low power consumption of these parts in normal operation makes them ideally suited to portable battery - operated equip - ment. the combination of small package and low power makes these nano dac devices ideal for level - setting requirements, such as generating bias or control voltages in space - constr ained and power - sensitive applications. product highlights 1. available in 6 - lead lfcsp and sc70 package s. 2. low power, single - supply operation. the ad5601/ ad5611/ad5621 operate from a single 2.7 v to 5.5 v supply with a maximum current consumption of 100 a , making them ideal for battery - powered applications. 3. the on - chip output buffer amplifier allows the output of the dac to swing rail - to - rail with a typical slew rate of 0.5 v/s. 4. reference is derived from the power supply. 5. high speed serial interface wit h clock speeds up to 30 mhz. designed for very low power consumption. the interface powers up only during a write cycle. 6. power - down capability. when powered down, the dac typically consumes 0.2 a at 3 v. power - on reset with brownout detection. ad5601/ad56 1 1/ad5621 v dd v out gnd power-on reset dac register 12-/10-/8-bit dac input contro l logic power-down contro l logic output buffer resis t or network ref(+) sclk sdin 06853-001 sync
ad5601/ad5611/ad5621 data sheet rev. f | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 prod uct highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 4 absolu te maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 terminology .................................................................................... 13 theory of operat ion ...................................................................... 14 dac section ................................................................................ 14 resistor string ............................................................................. 14 output ampli fier ........................................................................ 14 serial interface ............................................................................ 14 input shift register .................................................................... 14 sync interrupt .......................................................................... 14 power - on reset .......................................................................... 16 power - down modes .................................................................. 16 microprocessor interfacing ....................................................... 16 applications ..................................................................................... 18 choosing a refer ence as power supply for the ad5601/ad5611/ad5621 ....................................................... 18 bipolar operation using the ad5601/ad5611/ad5621 ..... 18 using the ad5601/ad5611/ad5621 with a galvanically isolated interface ........................................................................ 19 power supply bypassing and grounding ................................ 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 21 r evision history 2 / 1 2 rev. e to rev. f added 6 - lead lfcsp ......................................................... universal changes to features section, general description section, table 1 , and product highlights section ....................................... 1 changes to table 4 ............................................................................ 5 added figure 4 ; renumbered sequentially .................................. 6 changes to table 5 ............................................................................ 6 changes to choosing a reference as power supply for the ad 5601 /ad 5611 /ad 5621 section .............................................. 18 updated outline dimensions ....................................................... 20 changes to ordering guide .......................................................... 21 7 /10 rev. d to rev. e changes to fi gure 1 .......................................................................... 1 5/08 rev. c to rev. d changes to general description section ...................................... 1 changes to table 2 ............................................................................ 3 changes to choosing a reference as power supply for the ad5601/ad5611/ad5621 section .............................................. 18 changes to ordering guide .......................................................... 20 12 /07 rev. b to rev. c changes to features .......................................................................... 1 changes to table 2 ............................................................................. 3 changes to ad 5601 /ad 5611 /ad 5621 to adsp - 2101 interface section ............................................................................. 16 updated outline dimensions ....................................................... 20 changes to ordering guide .......................................................... 20 7/05 rev. a to rev. b changes to figure 48 ...................................................................... 17 changes to galvanically isolated interface section ................... 19 changes to figure 52 ...................................................................... 19 3/05 rev. 0 to rev. a changes to timing characteristics ................................................. 4 changes to absolute maximum ratings ........................................ 5 change s to full scale error section ................................................ 7 changes to figure 20 ...................................................................... 10 ch anges to theory of operation .................................................. 14 changes to power down modes .................................................. 15 1/05 revision 0: initial version
data sheet ad5601/ad5611/ad5621 rev. f | page 3 of 24 specifications v dd = 2.7 v to 5.5 v; r l = 2 k? to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted. temperature range for a/b grades is ?40c to +125c, typical at 25c. table 2 . a grade b grade parameter min typ max min typ max unit test conditions/comments static performance ad5601 resolution 8 bits relative accuracy 1 (inl) 0.5 lsb differential nonlinearity (dnl) 0.5 lsb guaranteed monotonic by design ad5611 resolution 10 bits relative accuracy 1 (inl) 4 0.5 lsb differential nonlinearity (dnl) 0.5 0.5 lsb guaranteed monotonic by design ad5621 resolution 12 bits relative accuracy 1 (inl) 6 1 lsb differential nonlinearity (dnl) 0.5 0.5 lsb guaranteed monotonic by design zero - code error 0.5 10 0.5 10 mv all 0s loaded to dac register full - scale error 0.5 0.5 mv all 1s loaded to dac register offset error 0.063 10 0.063 10 mv gain error 0.0004 0.037 0.0004 0.037 %fsr zero - code error drift 5.0 5. 0 v/c gain temp erature coefficient 2.0 2. 0 ppm fsr/c output characteristics 2 output voltage range 0 v dd 0 v dd v output voltage settling time 6 10 6 10 s code ? scale to ? scale slew rate 0.5 0. 5 v/ s capacitive load stability 470 470 pf r l = 1000 1000 pf r l = 2 k output noise spectral density 120 120 nv/ hz dac code = midscale,1 khz noise 2 2 v dac code = midscale, 0.1 hz to 10 khz bandwidth digital -to - analog glitch impulse 5 5 nv - s 1 lsb change around major carry digital feedthrough 0.2 0.2 nv - s short - circuit current 15 15 ma v dd = 3 v/5 v dc output impedance 0.5 0.5 logic inputs input current 3 2 2 a input high voltage , v inh 1.8 1.8 v v dd = 4.7 v to 5.5 v 1.4 1.4 v v dd = 2.7 v to 3.6 v input low voltage , v inl 0.8 0.8 v v dd = 4.7 v to 5.5 v 0.6 0.6 v v dd = 2.7 v to 3.6 v pin input capacitance 3 3 pf
ad5601/ad5611/ad5621 data sheet rev. f | page 4 of 24 a grade b grade parameter min typ max min typ max unit test conditions/comments power requirements v dd 2.7 5.5 2.7 5.5 v all digital inputs at 0 v or v dd i dd for normal mode dac active and excluding load current v dd = 4.5 v to 5.5 v 75 100 75 100 a v ih = v dd and v il = gnd v dd = 2.7 v to 3.6 v 60 90 60 90 a v ih = v dd and v il = gnd i dd for all power - down modes v ih = v dd and v il = gnd v dd = 4.5 v to 5.5 v 0.5 0.5 a v ih = v dd and v il = gnd v dd = 2.7 v to 3.6 v 0.2 0.2 a v ih = v dd and v il = gnd power efficiency i out /i dd 96 96 % i load = 2 ma and v dd = 5 v 1 linearity calculated using a reduced code range : ad5621 from code 64 to code 4032; ad5611 from code 16 to code 1008; ad5601 from code 4 to code 252. 2 guaranteed by design and characterization, not production tested. 3 total current flowing into all pins. timing characteristi cs v dd = 2.7 v to 5.5 v; all specifications t min to t max , unless otherwise noted. see figure 2 . table 3 . parameter limit 1 unit test conditions/comments t 1 2 33 ns min sclk cycle time t 2 5 ns min sclk high time t 3 5 ns min sclk low time t 4 10 ns min sync to sclk falling edge setup time t 5 5 ns min data setup time t 6 4.5 ns min data hold time t 7 0 ns min sclk falling edge to sync rising edge t 8 20 ns min minimum sync high time t 9 13 ns min sync rising edge to next sclk falling edge ignored 1 all input signals are specified with tr = tf = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 2 maximum sclk frequency is 30 mhz. figure 2 . timing diagram t 4 t 3 t 2 t 5 t 7 t 6 d0 d1 d2 d14 d15 sync sclk 06853-002 t 9 t 1 t 8 d15 d14 sdin
data sheet ad5601/ad5611/ad5621 rev. f | page 5 of 24 absolute maximum rat ings t a = 25c, unless otherwise noted. table 4 . parameter rating v dd to gnd ?0.3 v to +7.0 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v v out to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial (a/b grades) ?40c to +125c storage temperature range ?65c to +160c maximum junction temperature 150c sc70 package ja thermal impedance 433.34c/w jc thermal impedance 149.47c/w lfcsp package ja thermal impedance 95c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c esd (human body model) 2.0 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied . exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5601/ad5611/ad5621 data sheet rev. f | page 6 of 24 pin configuration and fu nction descriptions figure 3. 6-lead sc70 pin configuration figure 4. 6-lead lfcsp pin configuration table 5. pin function descriptions sc70 pin no. lfcsp pin no. mnemonic description 1 4 sync level-triggered control input (active low). this is the frame synchronization signal for the input data. when sync goes low, it enables the input shift register , and data is transferred in on the falling edges of the clocks that follow. the dac is updated following the 16 th clock cycle, unless sync is taken high before this edge, in which case the rising edge of sync acts as an interrupt and the write sequence is ignored by the dac. 2 2 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data can be transferred at rates up to 30 mhz. 3 3 sdin serial data input. this device has a 16-bit shift regist er. data is clocked into the register on the falling edge of the serial clock input. 4 1 v dd power supply input. the ad5601/ad5611/ad5621 can be operated from 2.7 v to 5.5 v. v dd should be decoupled to gnd. 5 5 gnd ground. ground reference point for all circuitry on the ad5601/ad5611/ad5621. 6 6 v out analog output voltage from the dac. the o utput amplifier has rail-to-rail operation. ep exposed pad. connect to gnd. ad5601/ ad5611/ ad5621 top view (not to scale) v out sync 16 gnd sclk 25 sdin v dd 34 06853-003 06853-053 1v dd 3 sdin 2 sclk notes: 1. connect the exposed pad to gnd. 6v out 5gnd 4sync top view (not to scale) ad5601/ ad5611/ ad5621
data sheet ad5601/ad5611/ad5621 rev. f | page 7 of 24 typical performance characteristics figure 5. typical ad5621 inl figure 6 . typical ad5611 inl figure 7 . typical ad5601 inl figure 8 . ad5621 total unadjusted error (tue) figure 9. ad5611 total unadjusted error (tue) figure 10 . ad5601 total unadjusted error (tue) ?1.0 ?0.5 0 0.5 1.0 dac code in l error (lsb) 06853-004 64 564 1064 1564 2064 2564 3064 3564 4064 v dd = v ref = 5v t a = 25c 0 16 1 16 216 316 416 516 616 716 816 916 dac code in l error (lsb) v dd = v ref = 5v t a = 25c 06853-005 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0.1 0.2 0.3 0.4 0.5 0 4 54 104 154 204 dac code in l error (lsb) v dd = v ref = 5v t a = 25c 06853-006 ? 0.100 ? 0.075 ? 0.050 ? 0.025 0.025 0.050 0.075 0.100 ?2.5 ?1.5 ?0.5 0.5 1.5 2.5 64 564 1064 1564 2064 2564 3064 3564 dac code total unadjusted error (lsb) 06853-007 0 1.0 2.0 ?2.0 ?1.0 v dd = v ref = 5v t a = 25c 4064 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 16 1 16 216 316 416 516 616 716 816 916 dac code total unadjusted error (lsb) 06853-008 v dd = v ref = 5v t a = 25c ?0.20 ?0.15 ?0.10 ?0.05 0.05 0.10 0.15 0.20 4 54 104 154 204 dac code total unadjusted error (lsb) 0 v dd = v ref = 5v t a = 25c 06853-009
ad5601/ad5611/ad5621 data sheet rev. f | page 8 of 24 figure 11 . typical ad5621 dnl figure 12 . typical ad5611 dnl figure 13 . typical ad5601 dnl figure 14 . i dd histogram (3 v/5 v) figure 15 . full - scale settling time figure 16 . half - scale settling time ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 64 564 1064 1564 2064 2564 3064 3564 dac code dn l error (lsb) v dd = 5v t a = 25c 0 06853-010 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0.05 16 1 16 216 316 416 516 616 716 816 916 dac code dn l error (lsb) v dd = 5v t a = 25c 06853-0 1 1 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0.010 4 54 104 154 204 dac code dn l error (lsb) 06853-012 v dd = 5v t a = 25c 0 2 4 6 8 10 12 0.05456 0.05527 0.05599 0.05671 0.05742 0.05814 0.05885 0.06648 0.06710 0.06773 0.06835 0.06897 0.06960 0.07022 0.07084 0.07147 0.07209 0.07271 0.07334 i dd (ma) number of devices 06853-013 v dd = 5v v ih = dv dd v il = gnd t a = 25c v dd = 3v v ih = dv dd v il = gnd t a = 25c ch1 = 5v/div ch2 = 1v/div time base = 2s/div ch1 = sclk ch2 = v out 06853-014 t a = 25c v dd = 5v ch1 = 5v/div ch2 = 1v/div time base = 2s/div ch1 = sclk ch2 = v out t a = 25c v dd = 5v 06853-015
data sheet ad5601/ad5611/ad5621 rev. f | page 9 of 24 figure 17. power-on reset to 0 v figure 18. v dd vs. v out figure 19. digital-to-analog glitch energy figure 20. 1/f noise, 0.1 hz to 10 hz bandwidth figure 21. exiting power-down mode figure 22. i dd vs. sclk vs. code ch2 ch1 06853-016 v dd = 5v t a = 25c v dd v out = 70mv ch1 1v, ch2 20mv, time base = 20s/div ch1 1v, ch2 5v, time base = 50s/div ch2 ch1 06853-017 v dd v out v dd = 5v t a = 25c sample number amplitude (v) 0 100 200 300 400 500 2.458 2.456 2.454 2.452 2.450 2.448 2.446 2.444 2.442 2.440 2.438 2.436 t a = 25c v dd = 5v load = 2k ? and 220pf code 0x2000 to 0x1fff 10ns/sample number 06853-018 06853-019 ch1 ch1 5v/div v dd = 5v t a = 25c midscale loaded ch1 5v, ch2 1v, time base = 2s/div ch1 ch2 06853-020 v dd = 5v t a = 25c v out 0 20 40 60 80 100 120 140 0 5 10 15 20 25 frequency (mhz) i dd (a) 06853-021 3/4 scale full scale 1/4 scale midscale zero scale
ad5601/ad5611/ad5621 data sheet rev. f | page 10 of 24 figure 23 . noise spectral density figure 24 . supply current vs. digital input code figure 25 . sink and source capability figure 26 . inl vs. temperature (5 v) figure 27 . dnl vs. temperature (5 v) figure 28 . zero - code error and full - scale error vs. temperature 0 100 200 300 400 500 600 700 100 1k 10k 100k frequency (hz) output noise spectral density (nv/ hz) v dd = 5v t a = 25c unloaded output midscale zero scale full scale 06853-022 0 10 20 30 40 50 60 70 0 2000 4000 6000 8000 10000 12000 14000 16000 digital input code i dd ( a) v dd = 5v v dd = 3v 06853-023 t a = 25c ?0.6 ?0.4 ?0.2 0.0 0.2 0.4 0.6 0.8 ?15 ?10 ?5 0 5 10 15 i (ma) v out (v) 06853-0 24 dac loaded with zero-scale code v dd = 5v t a = 25c dac loaded with full-scale code ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 ?40 ?20 0 40 20 60 80 100 120 temperature (c) inl error (lsb) 06853-025 ad5611 min inl error ad5621 min inl error ad5621 max inl error v dd = 5v ad5611 max inl error ad5601 max inl error ad5601 min inl error ?0.08 ?0.07 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 ?40 10 60 110 160 temperature (c) dnl error (lsb) v dd = 5v 06853-026 ad5611 min dnl error ad5621 max dnl error ad5611 max dnl error ad5601 max dnl error ad5601 min dnl error ad5621 min dnl error ?40 40 60 80 100 ?20 0 ?20 120 140 temperature (c) error (lsb) ad5621 zero-code error ad5611 full-scale error ad5621 full-scale error v dd = 5v 06853-027 0.00149 0.00099 0.00049 ?0.00001 ?0.00051 ad5611 zero-code error ad5601 zero-code error ad5601 full-scale error
data sheet ad5601/ad5611/ad5621 rev. f | page 11 of 24 figure 29 . total unadjusted error (tue) vs. temperature (5 v) figure 30 . offset error vs. temperature ( 3 v/ 5 v suppl y ) figure 31 . gain error vs. temperature ( 3 v/ 5 v supply ) figure 32 . supply current vs. temperature ( 3 v/ 5 v supply ) figure 33 . inl vs. supply voltage at 25c figure 34 . dnl vs. supply voltage at 25c ?0.5 ?0.3 ?0.1 0.1 0.3 0.5 1.5 ?40 ?20 temperature (c) total unadjusted error (lsb) ad5601 min tue ad5611 min tue ad5621 min tue 06853-028 0.7 0.9 1.1 1.3 0 20 40 60 80 100 120 140 ad5621 max tue ad5601 max tue ad5611 max tue 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.1 1.2 1.3 1.4 1.5 ?40 ?20 0 20 100 120 140 temperature (c) offset error (mv) 40 60 80 1.0 v dd = 5v v dd = 3v 06853-029 ?0.016 ?0.014 ?0.012 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) gain error (%fsr) v dd = 3v v dd = 5v 06853-030 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) i dd (ma) v dd = 3v v dd = 5v 06853-031 2.7 3.2 3.7 4.2 4.7 5.2 supply voltage (v) inl error (lsb) t a = 25c 06853-032 ad5621 max inl error ad5611 min inl error ad5621 min inl error ad5611 max inl error ad5601 min inl error ad5601 max inl error ?0.6 ?0.4 ?0.2 0 0.2 0.4 ?0.10 ?0.09 ?0.08 ?0.07 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 2.7 3.2 3.7 4.2 4.7 5.2 5.7 6.2 6.7 supply voltage (v) dnl error (lsb) 0 t a = 25c ad5621 max dnl error ad5601 max dnl error ad5601 min dnl error ad5621 min dnl error 06853-033 ad5611 max dnl error ad5611 min dnl error
ad5601/ad5611/ad5621 data sheet rev. f | page 12 of 24 figure 35 . total unadjusted error (tue) vs. supply voltage at 25c figure 36 . zero - code error and full - scale error vs. supply voltage at 25c figure 37 . supply current vs. supply voltage at 25c figure 38 . sclk/sdin vs. logic voltage 2.7 3.2 3.7 4.2 4.7 5.2 supply voltage (v) total unadjusted error (lsb) t a = 25c ad5621 max tue ad5601 max tue ad5611 min tue ad5601 min tue ad5621 min tue 06853-034 ?0.3 ?0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 ad5611 max tue 2.7 3.2 3.7 4.2 4.7 5.2 5.7 6.2 6.7 supply voltage (v) error (lsb) t a = 25c ad5621 zero-code error ad5611 zero-code error ad5621 full-scale error ad5611 full-scale error ad5601 zero-code error ad5601 full-scale error 06853-035 ?0.0004 ?0.0002 0 0.0002 0.0004 0.0006 0.0008 0.0010 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 2.7 3.2 3.7 4.2 4.7 5.2 supply voltage (v) i dd ( m a) t a = 25c 06853-036 0 50 100 150 200 250 300 350 400 450 0 v logic (v) i dd (a) sclk/sdin increasing v dd = 3v sclk/sdin decreasing v dd = 3v sclk/sdin decreasing v dd = 5v sclk/sdin increasing v dd = 5v 6 4 5 3 2 1 t a = 25c 06853-0 37
data sheet ad5601/ad5611/ad5621 rev. f | page 13 of 24 terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer func - tion. see figure 5 to figure 7 for plots of typical inl vs. code. differential nonlinearity differential non linearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. see figure 11 to figure 13 for plots of typical dnl vs. code. zero - code error zero - code error is a measure of the output error when zero code (0x0000) is loaded to the dac register. ideally, the output should be 0 v. the zero - code error is always positive in the ad5601/ad5611/ad562 1 because the output of the dac cannot go below 0 v. z e r o - code error is due to a combination of the offset errors in the dac and output amplifier. zero - code error is expressed in mv. see figure 28 for a plot of zero - code error vs. temperature. full - scale error full - scale error is a measure of the output error when full - scale code (0xffff) is loaded to the dac register. ideally, the output should be v dd ? 1 lsb. full - scale error is expressed in mv. see figure 28 for a plot of full - scale error vs. temperature. gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal, expressed as a percent of the full - scale range. total unadjusted error total unadjusted error (tue) is a measure of the output error, taking all the v arious errors into account. see figure 8 to figure 10 for plots of typical tue vs. code. zero - code error drift zero - code error drift is a measure of the change in zero - code error with a change in temperature. it is expressed in v/c. gain temperature coefficient gain temperature coefficient is a me asure of the change in gain error with changes in temperature. it is expressed in (ppm of full - scale range)/c. digital -to - analog glitch impulse digital - to - analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv - s and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x2000 to 0x1fff). see figure 19. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv - s and is measured with a full - scale code change on the data bus from all 0s to all 1s and vice versa.
ad5601/ad5611/ad5621 data sheet rev. f | page 14 of 24 theory of operation dac section the ad5601/ad5611/ad5621 dacs are fabricated on a cmos process. the architecture consists of a string dac followed by an output buf fer amplifier. figure 39 is a block diagram of the dac architecture. figure 39 . dac architecture because the input coding t o the dac is straight binary, the ideal output voltage is given by ? ? ? ? ? ? = n dd out d v v 2 where : d is the decimal equivalent of the binary code tha t is loaded to the dac register. n is the bit resolution of the dac. resistor string the resistor string structure is shown in figure 40 . it is simply a string of resistors, each of v alue r. the code loaded to the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaran - teed monotonic. figure 40 . resistor string structure output amplifier the output buffer amplifier is capable of generating rail - to - rail voltages on its output, giving an output range of 0 v t o v dd . it is capable of driving a load of 2 k? in parallel with 1000 pf to gnd. the source and sink capabilities of the output amplifier are shown in figure 25 . the slew rate is 0.5 v/s, with a half - scale settling time of 8 s with the output loaded. serial interface the ad5601/ad5611/ad5621 have a 3 - wire serial interface ( sync , sclk, and sdin) that is compatible with spi, qspi, an d microwire interface standards as well as most dsps. see figure 2 for a timing diagram of a typical write sequence. the write sequence begins by brin ging the sync line low. data from the sdin line is clocked into the 16- bit shift register on the falling edge of sclk. the serial clock frequency can be as high as 30 mhz, making the ad 5601 /ad 5611 /ad 5621 com - patible with high speed d sps. on the 16 th falling clock edge, the last data bit is clocked in and the programmed function is executed (a change in dac register contents and/or a change in the mode of operation). at this stage, the sync line may be kept low or brought high. in either case, it must be brought high for a minimum of 33 ns before the next write sequence so that a falling edge of sync can initiate the next write sequence. because the sync buffer draws more current when v in = 1.8 v than it does when v in = 0.8 v, sync should be idled low between write sequences for even lower power operation of the part, as mentioned previously. however, it must be brought high again j ust before the next write sequence. input shift register the input shift register is 16 bits wide (see figure 41 ). the first two bits are control bits, which control the operating mode of the part (normal mode or any one of three power - down modes). for a complete description of the various modes, see the power - down modes section. for the ad 5621 , the next 12 bits are the data bits, which are transferred to the dac register on the 16 th falling edge of sclk. the information in the last two bits is ignored by the ad5621. see figure 42 and figure 43 for the ad5611 and ad5601 input shift register map. sync interrupt in a normal write sequence, the sync line is kept low for at least 16 falling edges of sclk and the dac is updated on the 16 th falling edge. however, if sync is brought high before the 16 th falling edge, this acts as an interrupt to the write sequence. the shift register is reset and the write sequence is seen as invalid. neither an update of the dac register contents nor a change in the o perating mode occurs (see figure 44). v dd v ou t gn d resistor network ref (+ ) ref (?) output amplifie r dac regis te r 06853-038 r r r r r to output amplifier 06853-039
data sheet ad5601/ad5611/ad5621 rev. f | page 15 of 24 figure 41 . ad5621 input register contents figure 42 . ad5611 input register contents figure 43 . ad5601 input register contents figure 44 . sync interrupt facility db15 (msb) pd1 pd0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x db0 (lsb) data bits power-down modes 0 1 0 1 0 0 1 1 normal operation 1k to gnd 100k to gnd three-state 06853-040 db15 (msb) pd1 pd0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x db0 (lsb) data bits power-down modes 0 1 0 1 0 0 1 1 normal operation 1k to gnd 100k to gnd three-state 06853-041 db15 (msb) pd1 pd0 d8 d7 d6 d5 d4 d3 d2 d1 x x x x x x db0 (lsb) data bits power-down modes 0 1 0 1 0 0 1 1 normal operation 1k to gnd 100k to gnd three-state 06853-042 06853-043 db15 db15 db0 db0 invalid write sequence: sync high before 16 th falling edge valid write sequence, output updates on the 16 th falling edge sync sclk sdin
ad5601/ad5611/ad5621 data sheet rev. f | page 16 of 24 power - on reset the ad5601/ad5611/ad5621 contain a power - on reset circuit that controls the output voltage during power - up. the dac register is filled with 0s and the output voltage is 0 v. it remains there until a valid write sequence is made to the dac. this is useful in applications in which i t is important to know the state of the dac output while it is in the process of powering up. power - down modes the ad5601/ad5611/ad5621 have four separate modes of operation. these modes are software - programmable by setting two bits (db15 and db14) in the control register. table 6 shows how the state of the bits corresponds to the operating mode of the device. table 6 . operating modes of the ad5601/ad5611/ad5621 db15 db14 operating mode 0 0 normal operation power - down mode s : 0 1 1 k to gnd 1 0 100 k to gnd 1 1 three - state when both bits are set to 0 , the part has normal power consumption of 100 a maximum at 5 v. however, for the three power - down modes, the supply current falls to typically 0.2 a at 3 v. not only does the supply current fall, but the output stage is also internally switched from th e output of the amplifier to a resistor network of known values. this has the advantage that the output impedance of the part is known while the part is in power - down mode. there are three different options: the output is connected internally to gnd throu gh a 1 k? resistor or a 100 k? resistor, or the output is left open - circuited (three - stated). figure 45 shows the output stage. figure 45 . output stage d uring power - down the bias generator, output amplifier, resistor string, and other associated linear circuitry are all shut down when power - down mode is activated. however, the contents of the dac register are unaffected when in power - down. the time to exit power - down is typically 13 s for v dd = 5 v and 16 s for v dd = 3 v. see figure 21 for a plot. microprocessor inter facing ad5601/ad5611/ad5621 to adsp - 2101 interface figure 46 shows a serial interface bet ween the ad 5601/ ad5611/ad5621 and th e adsp - 2101 . the adsp - 2101 should be set up to operate in sport transmit alternate framing mode. the adsp - 2101 sport is programmed through the sport control register and should be configured as follows: internal clock operation, active low framing, and 16 - bit word length. transmission is initiated by writing a word to the tx register after the sport is enabled. figur e 46 . ad5601/ad5611/ad5621 to adsp - 2101 interface ad5601/ad5611/ad5621 to 68hc11/68l11 interface figure 47 shows a seria l interface between the ad5601/ ad5611/ ad5621 and the 68hc11/68l11 microcontroller. sck of the 68hc11/68l11 drives the sclk of the ad 5601/ ad5611/ ad5621, while the mosi output drives the serial data line of the dac. the sync signal is derived from a port line (pc7). the setup conditions for correct operation of this inter face are as follows: the 68hc11/68l11 should be configur ed so that the cpol bit is 0 and the cpha bit is 1. when data is being trans - mitted to the dac, the sync line is taken low (pc7). when the 68hc11/68l11 are configured as indicated , data appearing on the mosi output is valid on the fa lling edge of sck. serial data from the 68hc11/68l11 is transmitted in 8 - bit bytes with only eight falling clo ck edges occurring in the trans mit cycle. data is transmitted msb first. to load data to the ad5601/ad5611/ ad5621, pc7 is left low after the firs t eight bits are transferred and a second serial write operation is performed to the dac. pc7 is taken high at the end of this procedure. figure 47 . ad5601/ad5611/ad5621 to 68hc11/68l11 interface power-down circuitr y resistor networ k v ou t resistor string d ac am plifie r 06853-044 ad5601/ad5611/ ad5621* *additional pins omitted for clarity tfs dt sclk sync sdin sclk 06853-045 adsp-2101* 68hc11/ 68l11* ad5601/ad5611/ ad5621* *additional pins omitted for clarity pc7 sck mosi sync sclk sdin 06853-046
data sheet ad5601/ad5611/ad5621 rev. f | page 17 of 24 ad5601/ad5611/ad5621 to blackfi n? adsp - bf53 x interface figure 48 shows a seria l i nterface between the ad5601/ ad5611/ ad5621 and the blackfin adsp - bf53x microproces sor. the adsp - bf53x processor family incorporates two dual - channel synchronous serial ports, sport1 and sport0, for serial and multiprocessor communications. using sport0 to connect to the ad5601/ad5611/ad5621, the setup for the interface is as follows: dt0pri drives the sdin pin of the ad5601/ad5611/ ad5621, while tsclk0 drives the sclk of the part. the sync is driven from tfs0. figure 48 . ad5601/ad5611/ad5621 to blackfin adsp - bf53x interface ad5601/ad5611/ad5621 to 80c51/80l51 interface figure 49 shows a serial interface between the ad5601/ ad5611/ad5621 and the 80c51/80l51 microcontroller. the setup for the interf ace is as follows: txd of the 80c51/80l51 drives sclk of the ad5601/ad5611/ad5621, while rxd drives the serial data line of the part. the sync signal is again derived from a bit programmable pin on the port. in this case, port line p 3.3 is us ed. when data is to be transmit ted to the ad5601/ad5611/ad5621, p3.3 is taken low. the 80c51/80l51 transmit data only in 8 - bit bytes; therefore, only eight falling clock edges occur in the transmit cycle. to load data to the dac, p3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. p3.3 is taken high following the completion of this cycle. the 80c51/80l51 output the serial data lsb first. the ad5601/ad5611/ad5621 req uire data with the msb as the first bit received. the 80c51/80l51 transmit routine should take this into account. figure 49 . ad5601/ad5611/ad5621 to 80c51/80l51 interface ad5601/ad5611/ad5621 to microwire interface figure 50 shows an interface between the ad5601/ad5611/ ad5621 and any microwire - compatible device. serial data is shifted out on the falling edge of the serial clo ck and is clocked into the ad5601/ad5611/ad5621 on the rising edge of the sk. figure 50 . ad5601/ad5611/ad5621 to microwire interface adsp-bf53x* ad5601/ad5611/ ad5621* *additional pins omitted for clarity dt0pri tsclk0 tfs0 sdin sclk sync 06853-047 80c51/80l51* ad5601/ad5611/ ad5621* *additional pins omitted for clarity p3.3 txd rxd sync sclk sdin 06853-048 microwire* ad5601/ad5611/ ad5621* *additional pins omitted for clarity cs sk so sync sclk sdin 06853-049
ad5601/ad5611/ad5621 data sheet rev. f | page 18 of 24 applications choosing a reference as power supply for the ad5601/ad5611/ad 5621 the ad5601/ad5611/ad5621 come in tiny lfcsp and sc70 package s with less than a 100 a supply current. because of this, the choice of reference depends on the application requirement s . for applications with space - saving requirements , the adr02 is recommended. it is available in an sc70 package and has excellent drift at 9 ppm/c (3 ppm/c in the r - 8 package) and provides ver y good noise performance at 3.4 v p - p in the 0.1 hz to 10 hz range . because the supply current required by the ad5601/ad5611/ ad5621 is extremely low, the parts are ideal for low supply applications. the adr395 voltage reference is recommended in this case. it requires less than 100 a of quiescent current and can, therefore, drive multiple dacs in one system, if required. it also pr ovides very good noise performance at 8 v p - p in the 0.1 hz to 10 hz range. figure 51 . adr395 as power supply to the ad5601/ad5611/ad5621 some recommended precision references for use as supplies to the ad5601/ad5611/ad5621 are listed in table 7 . table 7 . precision references for the ad5601 / ad5611 / ad5621 part no. initial accuracy (mv max) temp drift (ppm/c max) 0.1 hz to 10 hz noise (v p - p typ) adr435 2 3 (r -8) 8 adr425 2 3 (r -8) 3.4 adr02 3 3 (r -8) 10 adr02 3 3 (sc70) 10 adr395 5 9 (tsot -23) 8 bipolar operation us ing the ad5601/ad5611/ad5621 the ad5601/ad5611/ad5621 have been designed for single - supply operation, but a bipolar output range is also possible using the circuit shown in figure 52 . the circuit in figure 52 gives an output voltage range of 5 v. rail - to - rail operation at the amplifier output is achievable us ing an ad820 or op295 as the output amplifier. figure 52 . bipolar operation with the ad5601/ad5611/ad5621 the output voltage for any input code can be calculated as ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = r1 r2 v r1 r2 r1 d v v dd n dd out 2 where d represents the input code in decimal (0 C 2 n ). with v dd = 5 v, r1 = r2 = 10 k? v 5 2 10 ? ? ? ? ? ? ? = n out d v this is an output voltage range of 5 v , with 0x0000 corre - sponding to a ?5 v output and 0x3fff corresponding to a +5 v output. 3-wire serial interface sync sclk sdin 7v 5v v out = 0v to 5v a dr395 06853-050 ad5601/ad5611/ ad5621 5 n 06853-051 +5 v ?5 v ad 820/ op295 3-wire serial interface +5 v ad5601/ad5611/ ad5621 10f 0. 1f v dd v out 5 n +5v
data sheet ad5601/ad5611/ad5621 rev. f | page 19 of 24 using the ad5601/ad5 611/ad5621 with a galvanically isolate d interface in process control applications in industrial environments, it is often necessary to use a galvanically isolated in terface to protect and isolate the controlling circuitry from any hazardous common - mode voltages that might occur in the area where the dac is functioning. i coupler? provides isolation in excess of 2.5 kv. because the ad5601/ad561 1/ad5621 use a 3 - wire seri al logic interface, the adum1300 3 - channel digital isolator provides the required isolation (see figure 53 ). the power supply to the part also needs to be isolated, which is done by using a transformer. on the dac side of the transformer, a 5 v regulator provides the 5 v supply required for the ad5601/ ad5611/ad5621. figure 53 . ad5601/ad5611/ad5621 with a galvanically isolated interface power supply bypassi ng and grounding when accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. the pcb containing the a d5601/ ad5611/ad5621 should ha ve separate analog and digital sections, each having its own ar ea of the board. if the ad5601/ ad5611/ad5621 are in a system where other devices require an agnd - to - dgnd connection, the connection should be made at one point only . this g round point should be as close as possible to the ad5601/ad5611/ad5621. the power supply to the ad5601/ad5611/ad5621 should be bypassed with 10 f and 0.1 f capacitors. the capacitors should be physically as close as possible to the device, with t he 0.1 f capacitor ideally right up against the device. the 10 f capacitors are the tantalum bead type. it is important that the 0.1 f capacitor have low effective series resistance (esr) and effective series inductance (esi), such as in common ceramic types of capacitors. this 0.1 f capacitor provides a low imped - ance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line itself should have as large a trace as possible to provide a low i mpedance path and reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals, if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects on the board. the best board layout tech - nique is the microstrip technique, where the component side of the board is dedicated to the ground plan e only and the signal traces are placed on the solder side. however, this is not always possible with a two - layer board. 06853-052 v dd ad5601/ ad56 1 1/ ad5621 adum1300 power 10f 0.1f gnd 5v regul a t or sclk v oa v out v ob sync v oc v ia v ib v ic sclk sdi dat a sdin
ad5601/ad5611/ad5621 data sheet rev. f | page 20 of 24 outline dimensions figure 54 . 6- lead thin shrink small outline transistor package [sc70] (ks - 6) dimensions shown in millimeters figure 55 . 6 - lead lead frame chip scale package [lfcsp _wd ] 2.00 3.00 mm body, very very thin, dual lead (cp - 6 - 5) dimensions s hown in millimeters 1 . 3 0 b s c compliant to jedec stand ards mo-203-ab 1 . 0 0 0 . 9 0 0 . 7 0 0 . 4 6 0 . 3 6 0 . 2 6 2 . 2 0 2 . 0 0 1 . 8 0 2 . 4 0 2 . 1 0 1 . 8 0 1 . 3 5 1 . 2 5 1 . 1 5 072809 -a 0 . 1 0 m a x 1 . 1 0 0 . 8 0 0 . 4 0 0 . 1 0 0 . 2 2 0 . 0 8 3 1 2 4 6 5 0 . 6 5 b s c coplanarity 0.10 sea ting plane 0 . 3 0 0 . 1 5 1.50 1.40 1.30 0.45 0.40 0.35 t op view 6 1 4 3 b o t t o m v i e w pin 1 index area sea ting plane 0.80 0.75 0.70 1.70 1.60 1.50 0.203 ref 0.05 max 0.00 min 0.65 ref e x p o s e d p a d pin 1 indica t or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration and function descriptio ns section of this data sheet. 10-18-2010-a 2.10 2.00 1.90 3.10 3.00 2.90 compliant t o jedec standards mo-229 coplanarity 0.08 0.20 min 0.35 0.30 0.25
data sheet ad5601/ad5611/ad5621 rev. f | page 21 of 24 ordering guide model 1 temperature range inl package description package option branding ad5601bksz - 500rl7 C 40c to +125c 0.5 lsb 6 - lead thin shrink small outline transistor package [sc70] ks -6 d3v ad5601bksz - reel7 C 40c to +125c 0.5 lsb 6 - lead thin shrink small outline transistor package [sc70] ks -6 d3v ad5601bcpz -rl7 C 40c to +125c 0.5 lsb 6 - lead lead frame chip scale package [lfcsp _wd ] cp -6 -5 89 ad5611aksz - 500rl7 C 40c to +125c 4.0 lsb 6 - lead thin shrink small outline transistor package [sc70] ks -6 d3u ad5611aksz - reel7 C 40c to +125c 4.0 lsb 6 - lead thin shrink small outline transistor package [sc70] ks -6 d3u ad5611acpz -rl7 C 40c to +125c 4.0 lsb 6 - lead lead frame chip scale package [lfcsp _wd ] cp -6 -5 8b ad5611bksz - 500rl7 C 40c to +125c 0.5 lsb 6 - lead thin shrink small outline transistor package [sc70] ks -6 d3t ad5611bksz - reel7 C 40c to +125c 0.5 lsb 6 - lead thin shrink small outline transistor package [sc70] ks -6 d3t ad5621aksz - 500rl7 C 40c to +125c 6.0 lsb 6 - lead thin shrink small outline transistor package [sc70] ks -6 d3s ad5621aksz - reel7 C 40c to +125c 6.0 lsb 6 - lead thin shrink small outline transistor package [sc70] ks -6 d3s ad5621acpz -rl7 C 40c to +125c 6.0 lsb 6 - lead lead frame chip scale package [lfcsp _wd ] cp -6 -5 88 ad5621bksz - 500rl7 C 40c to +125c 1.0 lsb 6 - lead thin shrink small outline transistor package [sc70] ks -6 d3r ad5621bksz - reel7 C 40c to +125c 1.0 lsb 6 - lead thin shrink small outline transistor package [sc70] ks -6 d3r eval - ad5621ebz evaluation board 1 z = rohs compliant part.
ad5601/ad5611/ad5621 data sheet rev. f | page 22 of 24 notes
data sheet ad5601/ad5611/ad5621 rev. f | page 23 of 24 notes
ad5601/ad5611/ad5621 data sheet rev. f | page 2 4 of 24 notes ? 2005 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06853 - 0- 2/12(f)

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